Released on = August 3, 2006, 12:24 am

Press Release Author = MataiTech LLC

Industry = Semiconductors

Press Release Summary = MataiTech’s NAUET automatically links IP blocks, generates
Verilog, VHDL, C, System C, design documentation and test code. It accelerates HDL
coding and C/C++ coding to quickly allow engineers to begin application, driver and
HDL development.

Press Release Body = Rancho Santa Margarita, California – August 2, 2006 – MataiTech
LLC today announced NAUET, an EDA tool that prevents bugs at the source.

Compatible with major EDA tools, MataiTech’s NAUET automatically links IP blocks,
generates Verilog, VHDL, C, System C, design documentation and test code. It
accelerates HDL coding and C/C++ coding to quickly allow engineers to begin
application, driver and HDL development. Designs created with NAUET Component Editor
are reusable as IP in later projects, and NAUET Design Assembler is used to link
multiple IP blocks into a single, larger design.

NAUET allows hardware, software and system engineers begin collaboration
immediately. It creates an environment where all disciplines of a project have the
correct information at all times. Progress is tracked as the product develops. As
registers and bits change meaning and functionality, that change is known by all.

“NAUET shortens schedule and reduces risk out by automatically creating the design
documentation, header files and baseline register test suite from a single input.
Without NAUET such items require careful attention to detail and lots of time to
keep in sync and are highly susceptible to consistency errors,” explained Aaron
Baranoff, VP-Engineering at MataiTech.

Serial design is now a thing of the past and time to market is cut dramatically
because software development can start as soon as a hardware engineer enters the
design into NAUET. Design testing can start at the beginning of the project and can
continue throughout the design process with co-simulation, System C models, and
register test code, all before the chip is delivered.

In addition, groups outside of the immediate engineering team will have access to
the latest documentation, permitting initial customers, Application Engineering and
Marketing to start their jobs sooner, and with known-good documentation and
software.

NAUET is MataiTech’s fourth generation design tool. It is being offered to the
public for the first time. NAUET is designed to lower engineering costs and have an
extremely fast return on investment. It was originally developed to help MataiTech’s
engineers do multi million gate, multi-CPU chips for video processing and
networking.

The NAUET Basic Version is initially available for less than $1000.00 per license.
MataiTech is a member of the SPIRIT Consortium and NAUET follows to the IP-XACT
standard.

About MataiTech
Located in Orange County California, MataiTech can bring designs to market faster
than anybody in the industry. Our core engineering team has been using
hardware/software co-simulation technology for years to help develop networking,
encryption, parallel processing, multi million gate ASICs, FPGAs and embedded
operating systems for all industries.

See www.mataitech.com for additional information.

Contact: Rob Fleck, MataiTech LLC., (rob@mataitech.com) (949) 226 - 7079

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MataiTech LLC and the MataiTech LLC logo are either registered trademarks or
trademarks of MataiTech LLC, in the United States and/or other jurisdictions.
All other trademarks are the property of their respective holders.


Web Site = http://www.mataitech.com

Contact Details = Rob Fleck
MataiTech LLC
6 Santa Nella
Rancho Santa Margarita, CA 92688
rob@mataitech.com
(949) 226 - 7079